Quantitative analysis of ultrashallow junction of sub-50 nm gate-length transistors: Junction depth, sheet resistance, short channel effects, and transistor performance

We analyzed causes of dopant loss in ultrashallow junction during complementary metal-oxide-semiconductor (CMOS) fabrication: (1) sputtering-out during ion implantation, (2) wet-etching removal in cleaning process, (3) outdiffusion, and (4) deactivation in post-thermal process. By using low energy electron induced x-ray emission spectrometry and other conventional analytic techniques such as four-point probe (FPP) and SIMS, the dopant losses are quantified. We developed a simple source/drain extension (SDE) sheet-resistance test structure to measure the actual sheet resistance of SDE to avoid sizable error due to FPP probe penetration. By comparing with CMOS electrical data, practical aspect of junction depth and sheet resistance is discussed in terms of short channel effects and on-state current. It is found that deactivation and wet-etching removal of arsenic dopant during cleaning process are the major factors in scaling of n-type transistor, while junction depth is the major one in scaling of p-type transistor.