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We describe a manufacturing method (US Patent No. 6,713,371) to enhance the grain size of polysilicon films prepared by solid phase crystallization of amorphous silicon films. This technique requires deposition of silicon nuclei between two layers of amorphous silicon films. Grain size is controllable by varying the density of nuclei. Film deposition and crystallization can be conducted with commercially available semiconductor equipments in a single batch. The method does not require extra manufacturing steps after low pressure chemical vapor deposition of silicon films other than solid phase crystallization, making it easy to integrate into a metal-oxide-silicon technology. This article discusses characteristics of polysilicon films and thin-film-transistor-silicon-oxide-nitride-oxide-silicon memory cells formed using the method. Many layers of such cells can be vertically stacked for ultrahigh density file storage applications.
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures (Volume:23 , Issue: 5 )
Date of Publication: Sep 2005