Electron projection lithography (EPL) is under active development, with potential applications at the sub 65 nm nodes. In order to meet the stringent error budgets in this regime, image placement (IP) errors induced by chucking the mask during e-beam patterning, metrology, and exposure must be characterized and minimized. The focus of this study is to assess the distortions induced in200-mm-diam EPL stencil masks by chucking during e-beam patterning and EPL exposure. High-throughput test masks (with 3.39 mm square membrane windows) were evaluated, to assess IP errors throughout a typical mask process flow. Finite element structural models were developed to simulate the response of the test mask during each processing step. Finally, the results of the analysis were used to identify and characterize the sources of IP errors.