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Influence of gate patterning on line edge roughness

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4 Author(s)
Leunissen, L.H.A. ; IMEC, Kapeldreef 75, B-3001 Leuven, Belgium ; Jonckheere, Rik ; Ronse, Kurt ; Derksen, Giljam B.

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It is shown by simulation that the line edge roughness (LER) on the gates causes fluctuations on transistor performance [J. A. Croon etal, “Line edge roughness: Characterization, modeling, and impact on device behavior,” Proceedings of the IEDM, 2002; “Experimental investigation of the impact of line-edge roughness on MOSFET performance and yield” (to be published)]. Efforts are underway to investigate the influence on device performance experimentally. In this article, the transfer of the LER of the resist pattern into the poly silicon layer is investigated. For the experimental setup isolated gate lines ranging between 50–180 nm were patterned with an e-beam lithography. The resist line patterns are generated with some additional programmed LER. After the e-beam lithography step the processing was continued with etching the poly-Si, resist strip, and SiON removal. Using an offline software analysis tool for the edge detection based on SEM pictures, it was possible to determine the influence of processing on both types of roughness. The analysis shows that the LER pattern is transferred to a large extent into the poly-Si. The 3σ-value roughness is influenced only slightly. The linewidth decreases approximately 10 nm between the two measurements (after litho and etch). This result is confirmed by linewidth measurements on a CD-SEM. An additional numerical study shows that the high frequency LER (period of a few nm) is smoothed out as the etching decreases the linewidth and thus erases small bumps. © 2003 American Vacuum Society.

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Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures  (Volume:21 ,  Issue: 6 )