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Reduction of silicon recess caused by plasma oxidation during high-density plasma polysilicon gate etching

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2 Author(s)
Vitale, S.A. ; Texas Instruments, P.O. Box 650311, Mail Stop 3736, Dallas, Texas 75265 ; Smith, B.A.

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Silicon loss during gate etch from the active region of a traditional complementary metal–oxide–semiconductor transistor is shown to take place through plasma oxidation of the silicon substrate during the overetch step. The plasma oxidation occurs by an ion-enhanced process with an activation energy of only 0.02 eV. This phenomenon is successfully modeled using the traditional Deal–Grove thermal oxidation model, with the inclusion of a depth-dependent reaction rate constant to incorporate the ion-enhancement effect. Plasma oxidation and silicon loss are reduced by using a shorter polysilicon over-etch time, lower source and bias power, lower substrate temperature, and lower O2 flow. A viable polysilicon over-etch process was developed that produced vertical gate profiles while reducing the silicon loss by 32%. © 2003 American Vacuum Society.

Published in:

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures  (Volume:21 ,  Issue: 5 )

Date of Publication:

Sep 2003

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