An electron spin resonance study has been carried out on (100)Si/SiOx/ZrO2 and (100)Si/Al2O3/ZrO2 stacks with nm-thin dielectric layers grown by the atomic layer chemical vapor deposition method at 300 °C. This reveals the Si dangling bond type centers Pb0, Pb1 as prominent defects at the (100)Si/dielectric interface in both types of structures. While reassuring for the Si/SiOx/ZrO2 case, this Pb0, Pb1 fingerprint, archetypal for the thermal (100)Si/SiO2 interface, indicates that the as-deposited (100)Si/Al2O3 interface is basically (100)Si/SiO2-like. Yet, as exposed by the salient spectroscopic properties of the Pb0, Pb1 defects, the interfaces are found to be in an enhanced (less relaxed) stress state, generally characteristic of low-temperature Si/SiO2 fabrication. The thermal behavior has been addressed by subjecting the sample stacks to heat treatments in vacuum or O2 ambient. Based on the Pb0, Pb1 criterion, it is found that standard thermal Si/SiO2 interface properties may be approached by appropriate anneali- - ng (≥650 °C) in vacuum in the case of Si/SiOx/ZrO2. Yet, O2 ambient is required for Si/Al2O3, indicating that the initial interface is too abrupt to enable thermal interfacial rearrangement without growth of an additional SiOx interlayer. A minimal SiOx interlayer thickness (0.5 nm) appears requisite. Thus, Si/high-κ metal oxide structures may be endowed with device quality interfaces with sub-nm thin SiOx interlayer, which may support the applicability of high-κ metal oxides. Obviously, though, the (inherent) occurrence of an SiOx interlayer will impair the minimal equivalent SiO2 thickness that may ultimately be realized with an envisioned high-κ material. © 2002 American Vacuum Society.