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100 nm gate hole openings for low voltage driving field emission display applications

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3 Author(s)
Choi, J.O. ; Flat Panel Display Laboratory, Orion Electric Company, ESRC Bldg., Room #319, Ajou University, Suwon, Kyonggi-Do 442-749, Korea ; Akinwande, A.I. ; Smith, H.I.

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A laser interference lithography (LIL) process has been developed for 100 nm gate hole openings of a Spindt-tip field emission cathode. A precursor structure of 200-nm-high and 100-nm-wide resist dots is made at every 200 nm square-grid center over a whole surface area of a substrate by using the LIL. The precursor is transferred to uniform arrays of chromium (Cr) gate holes by using a trilayer resist process. For pixellation of emitter tips, oxide via holes are formed through selected areas of the gate metal holes to prepare a real estate which is to be occupied by molybdenum (Mo) tip emitters. Emission current densities of 0.01 and 10 mA/cm2 have been obtained at gate bias voltages of 10 and 20 V, respectively, from the emitters with a packing density of 2.5×109tips/cm2. These results suggest that cheaper and lower voltage driving electronics can be used for field emission displays by scaling the gate hole openings down to 100 nm. Manufacturing issues related to the trilayer resist process for the gate hole openings, parting layer deposition, and Mo-tip formation are discussed. © 2001 American Vacuum Society.

Published in:

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures  (Volume:19 ,  Issue: 3 )