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VLSI implementation of multiprocessor system

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2 Author(s)
Kang, J.-W. ; Syst. Res. Dept., Electron. & Telecommun. Res. Inst., Daejeon, South Korea ; Kee-Wook Rim

Integrating multiple processors into a chip is one of the leading technologies in computer architecture. This paper describes EMPC-96 which is an on-chip multiprocessor with shared cache architecture. Four integer units, data cache, instruction cache, dispatcher, and system interfaces are integrated into single chip. 400 MIPS is a target of the performance of this design

Published in:

Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on

Date of Conference:

6-10 Nov 1995