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HDTV level MPEG2 video decoder VLSI

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5 Author(s)
Onoye, T. ; Dept. of Inf. Syst. Eng., Osaka Univ., Japan ; Masaki, T. ; Morimoto, Y. ; Sato, Y.
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A novel architecture for an HDTV level MPEG2 decoder is developed, which consists of specific functional macrocells and macroblock level pipeline buffers. Owing to the sophisticated I/O interface among macrocells, macroblock level pipeline buffers are successfully incorporated with functional macrocells. A new organization of frame memory and interface is also devised. The designed decoder contains 454 K transistors, and occupies 81.0 mm2 with a 0.6 μm triple-metal CMOS technology

Published in:

Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on

Date of Conference:

6-10 Nov 1995

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