Referenced Items are not available for this document.
A full digital self-timed clock generation scheme is developed, where multiple internal clocks are self-generated for each external request. The internal clock period is designed to be the critical path delay of the internal system at all operating environments. This scheme can be applied to time-multiplexed implementations, self-timed operation, and low-power applications
Published in:
Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on
Date of Conference: 6-10 Nov 1995
- Page(s):
- 319 - 322
- Meeting Date :
- 06 Nov 1995-10 Nov 1995
- Print ISBN:
- 0-7803-2624-5
- INSPEC Accession Number:
- 5256391
- Digital Object Identifier :
- 10.1109/TENCON.1995.496404
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
