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Low power CMOS digital circuit design methodologies with reduced voltage swing

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5 Author(s)
T. S. Cheung ; Dept. of Electron. Eng., Tokyo Univ., Japan ; K. Asada ; K. L. Yip ; H. Wong
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In this paper, two techniques on low power circuit design, namely, clock separated logic and sub-Vdd voltage-swing interfacing, are introduced. In the former method, reduced voltage-swing at internal nodes is used to achieve relatively low power dissipation as compared to circuits with full voltage-swing. In the latter method, pass-transistor logic with suppressed internal voltage-swing is used to reduce power dissipation in the pass-transistor chain. Basic techniques on design of these circuits are investigated and analyzed

Published in:

Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on

Date of Conference:

6-10 Nov 1995