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A 70 MS/s 8-bit differential switched-current CMOS A/D converter using parallel interleaved pipelines

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4 Author(s)
M. Bracey ; Dept. of Electron. & Comput. Sci., Southampton Univ., UK ; W. Redman-White ; J. B. Hughes ; J. Richardson

A 70 MS/s CMOS A/D converter is presented. Four double-sampling differential switched-current pipelines are used in a time interleaved structure to achieve a high sampling rate. Particular issues addressed are the matching of signal copies whilst maintaining full analogue bandwidth, and minimising signal corruption during propagation. The experimental converter is fabricated in a standard 0.8 μm 5 V digital CMOS process without special options

Published in:

Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on

Date of Conference:

6-10 Nov 1995