By Topic

A new CMOS analog multiplier with improved input linearity

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Xiang-Luan Jia ; Dept. of Electron Sci., Nankai Univ., Tianjin, China ; Wei Huang ; Shi-Cai Qin

A new CMOS four-quadrant analog multiplier is presented. By means of an unique nonlinear compensation technique, the linear input range of the multiplier is extended significantly. The simulation results show that, when Vy=±3V, the nonlinear error is less than 0.94% over the ±3V input range of Vx and when Vx =±3V, the nonlinear error is less than 0.25% over the ±3V input range of Vy, with a power supply of ±5V

Published in:

Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on

Date of Conference:

6-10 Nov 1995