This article reports on the fabrication of single crystal silicon, field emission tip arrays. The tips are formed by exposing a ‘‘capped’’ silicon pedestal to a lateral high temperature thermal oxidation. Tips formed using this process have uniform height and profile, and have small radii of curvature—typically less than 20 nm. We have fabricated tip arrays with up to 2500 elements and with the tip‐to‐tip spacing ranging from 1.0 to 5.0 μm. The thermal SiO2 has a nominal thickness of 600 nm and serves as insulation between the extraction grid and the substrate. The extraction grid is a self‐aligned, sputter deposited Ti0.1W0.9 film. Extraction grid apertures range from 900 nm to 1.7 μm. The process sequence is flexible allowing the fabrication of tips with different heights. The vertical position of the tip apex with respect to the extraction grid aperture, therefore, is a controllable parameter. The preliminary emission measurements are presented here for arrays containing 400 elements. All testing is done in ultrahigh vacuum (typically less than 5.0×10-10 Torr). The areas of the arrays fabricated range from 40 μm×40 μm to 100 μm×100 μm. The tip heights range from 1.0 to 1.4 μm above the substrate silicon. The maximum current produced from a 400 element array is only 0.45 μA at 140 Vdc. The low array current indicates that only a small number of tips are active at a given voltage.