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Large area silicon on insulator by double‐merged epitaxial lateral overgrowth

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2 Author(s)
Subramanian, Chitra K. ; School of Electrical Engineering, Purdue University, West Lafayette, Indiana 47907 ; Neudeck, Gerold W.

Your organization might have access to this article on the publisher's site. To check, click on this link:http://dx.doi.org/+10.1116/1.586425 

The process and feasibility verification for a full wafer silicon‐on‐insulator (SOI) process by using two merged epitaxial lateral overgrowths has been achieved. This process can be used to produce SOI material with a wide range of silicon thicknesses from 0.1 μm to several microns thick and is compatible with three‐dimensional circuit integration. Formation of local area SOI islands, formation of vertical wall seed windows, and epitaxial lateral overgrowth from these narrow vertical seeds have been demonstrated. This SOI process has the potential to reduce the defect density and cost of SOI substrates.

Published in:

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures  (Volume:10 ,  Issue: 2 )

Date of Publication:

Mar 1992

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