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A HW/SW Co-Verification Technique for Field Programmable Gate Array (FPGA) Test

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5 Author(s)
Y. B. Liao ; State key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu ; P. Li ; A. W. Ruan ; Y. W. Wang
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Field programmable gate arrays (FPGAs) have wide and extensive applications in many areas. Due to programmable feature of FPGAs, faults of FPGAs can be easily tolerated if fault sites can be located. A hardware/software (HW/SW) co- verification technique for FPGA test is proposed and presented in the paper. Taking advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware, this technique is capable of testing each input/output block (IOB) and configurable logic block (CLB) of FPGA automatically, exhaustively and repeatedly. Fault cells of FPGA can be positioned automatically by the proposed approach. As a result, test efficiency and reliability can be enhanced without manual work.

Published in:

2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis

Date of Conference:

28-29 April 2009