By Topic

ASIC design validation in a system context

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
J. Bartlett ; Sylvan Technol. Inc., USA

The paper describes a methodology for ASIC design validation in a system simulation context. The methodology is based on using a single system level testbench across all levels of model abstraction and throughout the entire product development cycle. Topics covered include how to design a system simulation for ASIC validation, elements of a good validation plan, writing a Verilog system level testbench and testing at different model abstraction levels. The paper uses Verilog design examples from two different projects to illustrate validation of both single and multiple ASIC systems. The benefits of following this methodology to a project's quality, time to market and predictability are shown

Published in:

Verilog HDL Conference, 1996. Proceedings., 1996 IEEE International

Date of Conference:

26-28 Feb 1996