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Small signal parameter analysis for UD DG FD SOI n-MOSFET has been performed using ATLAS 3-D device simulator. It is found from the analysis that gate misalignment causes degradation in ac characteristics i.e. capacitance and cut-off frequency of the device. Using graded channel architecture i.e. high-low doping profile reduces/eliminate the effect of gate misalignment and thus improves the device performance.