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High tolerance to gate misalignment in graded channel double gate SOI n-MOSFETs: Small signal parameter analysis

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3 Author(s)
Rupendra Kumar Sharma ; Semiconductor Devices Research Laboratory, Department of Electronic Science, University of Delhi South Campus, New Delhi 110021, India ; Mridula Gupta ; R. S. Gupta

Small signal parameter analysis for UD DG FD SOI n-MOSFET has been performed using ATLAS 3-D device simulator. It is found from the analysis that gate misalignment causes degradation in ac characteristics i.e. capacitance and cut-off frequency of the device. Using graded channel architecture i.e. high-low doping profile reduces/eliminate the effect of gate misalignment and thus improves the device performance.

Published in:

2008 Asia-Pacific Microwave Conference

Date of Conference:

16-20 Dec. 2008