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The CCS TL, is applied to the design of the multi-stage TL-based amplifier for the improvement on the gain-area efficiency. The design of a four-stage CS amplifier, which includes the circuit design and layout implementations, is reported in details. The presented design is fabricated by using the standard 0.18-mum CMOS technology. The on-chip measured results shows the gain and noise figure are exceeding 15 dB and smaller than 8 dB from 22 GHz to 26 GHz. The four-stage amplifier consumes a quiescent current of 21 mA with a supply voltage of 1.8 V. The input P1dB_IN and IIP3 are -15.6 dBm and -9.6 dBm at 23.85 GHz, respectively. Based on the measured results, the statistic results show that the improvement on gain-area efficiency of the prototype based on the proposed methodology can be observed.