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This paper introduces techniques for power-efficient design of power-delivery network (PDN) in multiple voltage-island system-on-chip (SoC) designs. The first technique is targeted to SoC designs with static-voltage assignment, while the second technique is pertinent to SoC designs with dynamic-voltage scaling (DVS) capability. Conventionally, a single-level configuration of dc-dc converters, where exactly one converter resides between the power source and each load, is used to deliver currents at appropriate voltage levels to different loads on the chip. In the presence of DVS capability, each dc-dc converter in this network should be able to adjust its output voltage. In the first part of this paper, it is shown that, in a SoC design with static-voltage assignment, a multilevel tree topology of suitably chosen dc-dc converters between the power source and loads can result in higher power efficiency in the PDN. The problem is formulated as a combinatorial problem and is efficiently solved by dynamic programming. In the second part of this paper, a new technique is presented to design the PDN for a SoC design to support DVS. In this technique, the PDN is composed of two layers. In the first layer, dc-dc converters with fixed output voltages are used to generate all voltage levels that are needed by different loads in the SoC design. In the second layer of the PDN, a power-switch network is used to dynamically connect the power-supply terminals of each load to the appropriate dc-dc converter output in the first layer. Experimental results demonstrate the efficacy of both techniques.