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Design Solutions for Sample-and-Hold Circuits in CMOS Nanometer Technologies

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5 Author(s)
Centurelli, F. ; Dipt. di Ing. Elettron., Univ. di Roma La Sapienza, Rome ; Monsurro, P. ; Pennisi, S. ; Scotti, G.
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Solutions for the design of low-voltage sample-and-hold (S/H) circuits in CMOS nanometer technologies are presented. As a design example, a 0.8-V supply S/H is designed and simulated using a 130-nm CMOS process. It dissipates 0.5 mW at dc and provides almost a rail-to-rail signal swing. When clocked at 40 MS/s and with a 1.4- VPP differential input signal, the simulated spurious-free dynamic range, signal-to-noise ratio, and total harmonic distortion are 57, 67, and -56 dB (9 equivalent bits), respectively, with low sensitivity to supply, temperature, process, and mismatch variations. The proposed solution employs a three-stage low-voltage amplifier without a tail current source in the differential pair and a switch topology, which combines clock voltage doubling and dummy switches.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:56 ,  Issue: 6 )