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Predicting the performance of a high-speed serial link for real world application requires a different approach to simulation than that traditionally used in slower systems. Given target bit error rates of 10-12 and lower, the ability to statistically confirm such performance in measurement, let alone simulation is challenging. For physically realistic interconnect and feasible silicon implementations, certain assumptions allow this problem to be solved with an analytical method in the so called statistical domain. The underlying assumption made to allow the problem to be treated statistically is one of superposition, which does not exclude the ability to analyze nonlinear or time variant problems. This work initially describes the basic theory of statistical signal analysis, and the latest extensions to this theory which allow correlated jitter and data problems to be studied. Simple code implementation are given together with a real world example, to help the reader understand the mathematical analysis and its application.