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On-Chip Measurement of Jitter Transfer and Supply Sensitivity of PLL/DLLs

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1 Author(s)
Jaeha Kim ; Stanford Univ., Stanford, CA

This brief describes low-cost on-chip measurement circuits for jitter transfer and supply sensitivity of phase-locked loops (PLLs) and delay-locked loops (DLLs). Unlike previous works that measured the frequency-domain responses, the proposed circuits measure the time-domain responses of the PLL/DLL to the periodic disturbances applied to either its input clock phase or its supply voltage. A synchronous sampling technique accurately measures the PLL/DLL's periodic response while suppressing the unrelated noises and interferences via averaging. The synchronous sampler outputs either DC voltage or digital values, making it suitable for low-cost characterization and production tests. The procedure for estimating the frequency-domain transfer functions from the measured time-domain responses is outlined. The jitter transfer and supply sensitivity measurements were demonstrated with a PLL fabricated in 0.13-mum CMOS. Compared with the PLL that occupied 1.1x0.46 mm2 and dissipated 36 mW from a 1.2-V supply, the on-chip measurement circuits occupied only 0.014 mm2 and dissipated only 2.6 mW.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:56 ,  Issue: 6 )

Date of Publication:

June 2009

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