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Interframe Bus Encoding Technique and Architecture for MPEG-4 AVC/H.264 Video Compression

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3 Author(s)
Bahari, A. ; Sch. of Microelectron. Eng., Univ. Malaysia Perlis, Arau, Malaysia ; Arslan, T. ; Erdogan, A.T.

In this paper, we propose an implementation of a data encoder to reduce the switched capacitance on a system bus. Our technique focuses on transferring raw video data for multiple reference frames between off- and on-chip memories in an MPEG-4 AVC/H.264 encoder. This technique is based on entropy coding to minimize bus transition. Existing techniques exploit the correlation between neighboring pixels. In our proposed technique, we exploit pixel correlation between two consecutive frames. Our method achieves a 58% power saving compared to an unencoded bus when transferring pixels on a 32-b off-chip bus with a 15-pF capacitance per wire.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:18 ,  Issue: 5 )