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Addendum to “Synthesis of robust delay-fault testable circuits: Theory”

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2 Author(s)
Devadas, S. ; Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA ; Keutzer, K.

For original paper see ibid., vol. 11, pp. 87-101 (Jan. 1992). The robust nature of the gate delay fault tests corresponding to Theorems 7 and 8 in the original paper is clarified and described in greater detail. There are two types of robust tests for gate delay faults: a hazard-free robust test for a gate delay fault on a gate g is a robust test where only paths that pass through g are event sensitized; a general robust test for a gate delay fault on a gate g is a robust test where paths that do not pass through g can be event sensitized. The two types of robust tests are illustrated

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:15 ,  Issue: 4 )