Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm

Automatic test pattern generation (ATPG) yielding high fault coverage for CMOS circuits has received a wide attention in industry and academia for a long time. Mixed level test pattern generation offers advantages, since test generation from gate-level netlists has shortcomings regarding fault coverage in complex CMOS gates. A switch-level approach relying on the transistor structure only is too slow and impractical for larger circuits. The first part of this paper describes ATPG with a mixed switch-level and gate-level approach. It combines acceptable performance for large networks with a high fault coverage as well as for nontrivial transistor networks. Patterns generated this way are inherently capable to detect stuck-open faults and transition faults as well as various other fault models on different abstraction levels. In combination with local overcurrent detectors, also stuck-on- and local bridging-faults can be identified. To increase the efficiency of mixed level test generation, a reconvergency analysis is performed and constraints are stored. The second part of this paper deals with mixed level test generation for synchronous sequential circuits. The FOGBUSTER (FOrward propaGation Backward jUstification Sequential Test genERation) algorithm is described and experimental results for the ISCAS '89 benchmark circuits are shown. FOGBUSTER makes use of a forward propagation technique which we show to be more efficient in general than the technique used in BACK