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The AMULET2e cache system

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3 Author(s)
Garside, J.D. ; Dept. of Comput. Sci., Manchester Univ., UK ; Temple, S. ; Mehra, R.

AMULET2e is an asynchronous microprocessor system based on the AMULET2 processor core. In addition to the processor it incorporates a number of distinct subsystems, the most notable of which is an asynchronous on-chip cache. This includes several novel features which exploit the asynchronous design style to increase throughput and reduce power consumption. These features are evident at a number of levels in the design. For example, the cache is micropipelined to increase its throughput, at the architectural level there is an arbitration free non-blocking line fetch mechanism while at the circuit design level there is a power-saving RAM sense amplifier control circuit. A significant property of the cache system is its ability to cycle in a data dependent way which allows the system to approach average case performance

Published in:

Advanced Research in Asynchronous Circuits and Systems, 1996. Proceedings., Second International Symposium on

Date of Conference:

18-21 Mar 1996