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Static scheduling of instructions on micronet-based asynchronous processors

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2 Author(s)
Arvind, D.K. ; Dept. of Comput. Sci., Edinburgh Univ., UK ; Rebello, V.

This paper investigates issues which impinge on the design of static instruction schedulers for micronet-based asynchronous processor (MAP) architectures. The micronet model exposes both temporal and spatial concurrency within a processor. A list scheduling algorithm is described which has been optimised with MAP-specific heuristics. Their performance on some program graphs are presented and conclusions are drawn on the suitability of MAP as targets for ILP compilers

Published in:

Advanced Research in Asynchronous Circuits and Systems, 1996. Proceedings., Second International Symposium on

Date of Conference:

18-21 Mar 1996

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