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VLSI architecture for motion estimation using the block-matching algorithm

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3 Author(s)
Sanz, C. ; Dept. de Sistemas Electronicos y de Control, Tech. Univ. of Madrid, Spain ; Garrido, M.J. ; Meneses, J.M.

In this paper an architecture is described that implements motion estimation in image coding, using a block-matching algorithm and an exhaustive search method. The architecture, EST256, consists of 256 processor elements, deals with a search area of -8/+7 and performs 11 GOPS (subtraction, absolute value determination, accumulation and comparison). It is implemented with ES2 0.7 μm double-metal-layer CMOS technology. This ASIC is cascadable to deal with bigger search areas

Published in:

European Design and Test Conference, 1996. ED&TC 96. Proceedings

Date of Conference:

11-14 Mar 1996