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A flexible gate array architecture for high-speed and high-density applications

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5 Author(s)
Gallia, J.D. ; Semicond. Process & Device Center, Texas Instrum. Inc., Dallas, TX, USA ; Landers, R.J. ; Shaw, C.-H. ; Blake, T.G.W.
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A scaleable gate array has been designed in half-micron CMOS for a wide range of high-speed and high-density applications. Transistor size and position within the basecell provide an efficient implementation of flip-flops, combinational gates, and memory. Design benchmarks have demonstrated 2700 gates/mm2 routed density in a 0.5 μm TLM CMOS gate array. Compared to previous 5 V 0.7 μm gate arrays, the new basecell provides improvements of 2.5x in density and 30% in speed, at 70% lower power, NAND-2 delays are 170 ps (FO=2, 3.3 V). Metal-programmable two-port SRAM's feature 3.9 ns typical access times. The new architecture has been implemented in a CMOS gate array family which offers up to 1.15 million available gates and 700 I/O positions

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Solid-State Circuits, IEEE Journal of  (Volume:31 ,  Issue: 3 )