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An 800-MHz 1-μm CMOS pipelined 8-b adder using true single-phase clocked logic-flip-flops

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2 Author(s)
Rogenmoser, R. ; Integrated Syst. Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland ; Qiuting Huang

An 8-b adder composed of carry-increment full adders has been designed and implemented in a standard 1.0 μm CMOS technology and successfully tested up to 800 MHz. The performance of this adder is based on a fine-grain pipeline technique using so called “logic-flip-flops”. These edge triggered logic-flip-flops are true single-phase clocked and reduce the cycle time of pipeline stages by combining logic and storage. For low power applications, the power consumption of the 8-b adder can be reduced from 777 mW (5 V Vdd, 800 MHz) down to 144 mW (3 V Vdd, 480 MHz)

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:31 ,  Issue: 3 )