By Topic

Low-supply-noise low-power embedded modular SRAM

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Schultz, K.J. ; Northern Telecom Electron. Ltd., Nepean, Ont., Canada ; Gibbins, R.G. ; Fujimoto, J.S. ; Phillips, R.S.
more authors

A low-noise, low-power embedded modular SRAM is described. A 512×15 configuration at 3.3 V generates a maximum of 8.2 mA/ns dI/dt and consumes 0.24 mW/MHz, the lowest power dissipation ever reported for a modular embedded memory. Results are achieved using a pulsed divided word line architecture, with internal cascaded clocks, weak static sensing, low-noise buffers and flip-flops and low-noise low-power decoding techniques. Alternatives in the core cell, sense amplifier and read/write architecture designs are discussed. Circuit details, as well as experimental and simulation results, are presented

Published in:

Circuits, Devices and Systems, IEE Proceedings -  (Volume:143 ,  Issue: 2 )