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The track-and-hold stage at the front-end of high-speed, high-resolution ADCs is usually the limiting factor in their linearity performance at high input frequencies. In this paper, we propose a digital correction algorithm for the dynamic errors generated in this stage. The digital post-processing scheme uses circuit insight and judicious modeling of the relevant nonidealities to minimize complexity. We show that the number of coefficients required in our model is significantly smaller than the number of coefficients in the general form of the Volterra series. The coefficients are extracted in a foreground calibration approach using least square (LS) solutions on a set of input and output samples from training signals. Simulation results on a nonlinear track-and-hold circuit model show approximately 40 dB of improvement in linearity (SFDR) until the fourth Nyquist zone (at fs = 100 MHz). The method was also applied to a commercially available 14-bit, 155-MS/s ADC and showed to improve its SFDR to more than 83 dB up to an input frequency of 470 MHz in a lab experiment.