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In this paper a novel user-friendly implementation of an all-digital phase-locked loop (ADPLL) is presented.Its novelty lies in the fact that the very basic functions of the ADPLL are kept in the top module Verilog file.Against the normal design practice, all of the main math functions were implemented using the sub-modules placed outside but called from within the top module.This way ADPLL can be easily implemented in a low-cost FPGA. Further, the implementation details of an ADPLL, which are not reported previously in a singles hot, are described altogether for the first time. The reconfigurable ADPLL is then implemented in a transceiver architecture and tested with real signals received wirelessly. The recovered IQ constellation EVM of 9.0336% was obtained, which is quite practical.This proves the feasibility of the ADPLL not only in simulations but in a real communication system. The ADPLL designed this way can be used in any communication system, although preferably for high data rate transceiver applications.