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The trend in high-speed digital circuits is to increase in speed and density, consume more current and to operate at lower voltage. This fast increase in the maximum current consumption and switching speed combined with the decrease of the operating voltage causes the allowable absolute voltage variations to decrease, which makes the PDS design a more challenging task than ever. Decoupling capacitors and power planes play a crucial role in maintaining the needed stability and accuracy of the PDS. More specifically, decoupling capacitors placement and value selection are the main parameters that are used to control the PDS behaviour. In this paper, we introduce a complete solution for the design of high-speed digital PDS. The proposed methodology covers the decoupling capacitor placement and value selection as well as an accurate methodology to check the full PDS performance and examine it against requirements. Finally, we applied our methodology to an industrial test case, compared its results to that industrial design, and showed its advantages.
Date of Conference: 6-9 April 2009