Cart (Loading....) | Create Account
Close category search window
 

A framework for estimating maximum power dissipation in CMOS combinational circuits using genetic algorithms

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Placer, J. ; Dept. of Comput. Sci. & Eng., Northern Arizona Univ., Flagstaff, AZ, USA ; Sagahyroon, A. ; Massoumi, M.

Assessing the maximum power dissipated by a CMOS combinational circuit is a complex problem because the power dissipated is input-pattern dependent. Simulation techniques are impractical, especially for large circuits, since the number of simulation runs needed increases exponentially with the number of inputs to the circuit. In this paper a genetic algorithm (GA) based approach is presented for generating a sequence of input vectors that tend to continuously maximize the switching activity of the circuit and hence the maximum power dissipated. The GA used evolves candidate input vectors while making use of a logic simulator to compute the fitness of each candidate. Experimentation with different GA parameters was carried out in order to derive an optimal set of working parameters for the GA. The performance of the GA technique was evaluated using “test circuits” whose topology allows simple analysis to determine the maximum number of simultaneous transitions possible for the circuits. In addition to this, some circuits from the ISAC-85 benchmark suite of circuits were also tested. The GA method was found to significantly out perform simulation-based techniques, especially in terms of CPU time expenditures

Published in:

System Theory, 1996., Proceedings of the Twenty-Eighth Southeastern Symposium on

Date of Conference:

31 Mar-2 Apr 1996

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.