One important issue for integrating atomic-layer-deposited (ALD) TaN barrier metal into Cu interconnects is a low thickness margin due to high electrical resistivity (∼50 mΩ cm) of ALD-TaN. In investigating this issue, the median via resistance (0.16 μm diameter vias) was found to increase from 0.5 to 26 Ω/via as the ALD-TaN thickness was increased from 1 to 2 nm. To reduce the resistivity of ALD-TaN, its atomic concentration on various substrates was investigated. The N/Ta ratio of ALD-TaN was found to be about 4/5 on a SiO2 substrate but about 1/2 on a Ta substrate. We also confirmed that the Ta-rich ALD-TaN film on the Ta substrate had low electrical resistivity (∼2 mΩ cm). We could thus successfully obtain low via resistance (5.4 Ω/via) with thick ALD-TaN (5 nm) by using a PVD-Ta/ALD-TaN/PVD-Ta multilayer structure.