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Sub-100 °C a-Si:H thin-film transistors on plastic substrates with silicon nitride gate dielectrics

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2 Author(s)
Sazonov, A. ; Electrical and Computer Engineering Department, University of Waterloo, Waterloo, Ontario N2L 3G1, Canada ; McArthur, C.

Your organization might have access to this article on the publisher's site. To check, click on this link:http://dx.doi.org/+10.1116/1.1784826 

Fabrication on thin-film transistors (TFTs) on flexible plastic substrates for large-area imagers and displays has been made possible by lowering the deposition temperatures, which reduces the thermal deformation of plastic substrates, greatly facilitating substrate preparation and device patterning. Furthermore, at extremely low deposition temperatures, much wider variety of low-cost substrates, plastics or otherwise, are available for use. In this article, we report on a-Si:H TFTs fabricated at 75 °C on glass and plastic substrates. The TFTs were fabricated using inverted–staggered topology, in a full wet etch process. The TFT structures consisted of 140 nm of sputtered Mo for gate, 380 nm of plasma-enhanced chemical vapor deposition (PECVD) a-SiNx:H gate dielectric optimized for 75 °C, 50 nm of PECVD a-Si:H channel material, 50 nm of PECVD n+ a-Si:H for source/drain contacts, and sputtered Al for contact metallization. Current–voltage characteristics were measured, and relevant transistor parameters were calculated. TFTs exhibited the leakage current below 10-12 A, and on/off current ratio exceeding 105. The results were compared to those for high temperature a-Si:H TFTs, and the differences are discussed.

Published in:

Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films  (Volume:22 ,  Issue: 5 )

Date of Publication:

Sep 2004

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