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Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations

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4 Author(s)
Amerasekera, A. ; Semicond. Process & Design Center, Texas Instrum. Inc., Dallas, TX, USA ; Ramaswamy, S. ; Chang, Mi-Chang ; Duvvury, C.

A circuit-level simulator for ESD and EOS is presented. Equations for modeling the high current behavior of NMOS and PMOS transistors have been developed and implemented in SPICE. A simple and practical extraction methodology for obtaining the bipolar parameters is given, which uses the three terminal currents obtained from a single high current I-V curve. Simulation results are presented and compared to experimental data for single devices as well as a practical output circuit.

Published in:

Reliability Physics Symposium, 1996. 34th Annual Proceedings., IEEE International

Date of Conference:

April 30 1996-May 2 1996

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