Quaterrylene field-effect transistors (FETs) with top-contact Au electrodes were formed on a SiO2 (200 nm)/p-Si (001) substrate by an ultraslow vacuum deposition technique, and their carrier transport was investigated. The quaterrylene FETs showed typical p-channel transistor behavior. The dependence of carrier mobility on grain size, film thickness, and temperature was examined to gain insight into the transport mechanism. Carrier mobility increased with grain size, showing that carrier transport was limited by grain boundaries. Temperature dependence in the range from 300 to 60 K was divided into two distinct behaviors. Above 210 K, carrier mobility showed thermally activated behavior, with energies of 100–150 meV required to overcome the potential barriers at grain boundaries. In contrast, the conduction mechanism became tunnel-transfer-like below 210 K. In the low temperature range, tunnel transfer through potential barriers at grain boundaries predominated over the thermally activated type. The change in carrier mobility was correlated with film thickness. Carrier mobility rose sharply with increasing thickness in the two-dimensional (2D) growth region, followed by saturation at 3 or 4 ML, where the growth process changed from 2D to three-dimensional mode. This result reveals that the first few layers of 2D growth work as an effective transistor channel. Enhancement in 2D growth in the vertical direction is crucial to improving carrier transport.