Strain optimization in ultrathin body transistors with silicon-germanium source and drain stressors

The potential of Si_1-xGe_x source and drain strained silicon p-channel transistors is investigated for ultrathin body silicon-on-insulator (SOI) substrates. We used process simulations to quantify and understand the role of device design parameters such as raised source and drain, source and drain length, and recess depth in the context of SOI transistors. Simultaneous strain calculations were performed with the process flow to capture not only lattice mismatch, but all process induced strain. Germanium condensation technique was found suitable for enhancing strain in ultrathin body transistors by increasing germanium concentration and driving germanium deeper into the source and drain. The scalability of germanium condensation process is discussed.