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Area-efficient reed-solomon decoder design for optical communications

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6 Author(s)
Bo Yuan ; Inst. of VLSI Design, Nanjing Univ., Nanjing ; Zhongfeng Wang ; Li Li ; Minglun Gao
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A high-speed low-complexity Reed-Solomon (RS) decoder architecture based on the recursive degree computationless modified Euclidean (rDCME) algorithm is presented in this brief. The proposed architecture has very low hardware complexity compared with the conventional modified Euclidean and degree computationless modified Euclidean (DCME) architectures, since it can reduce the degree computation circuitry and replace the conventional systolic architecture that uses many processing elements (PEs) with a recursive architecture using a single PE. A high-throughput data rate is also facilitated by employing a pipelining technique. The proposed rDCME architecture has been designed and implemented using SMIC 0.18-mum CMOS technology. Synthesized results show that the proposed RS (255, 239) decoder requires only about 18 K gates and can operate at 640 MHz to achieve a throughput of 5.1 Gb/s, which meets the requirement of modern high-speed optical communications.

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IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:56 ,  Issue: 6 )