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In this paper, we present a new decoder architecture for first-order sigma-delta analog-to-digital converters. This architecture is based on a dynamic decoding algorithm which is proposed to optimize the number of iterations required to decode sequences generated by the modulator, regardless of the conventional decoder. Optimization is achieved by an iterative algorithm that reduces the number of iterations using previously decoded values. The simulation results show a four-fold improvement over conventional decoding approaches and a gain of 1.69 dB for an 80-bit sequence and 4.01 dB for an 8-bit sequence regarding the decoding cycles. The proposed technique is implemented and tested on an field-programmable gate-array (FPGA) platform.