By Topic

Fabrication and testing of through-silicon vias used in three-dimensional integration

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Abhulimen, I.U. ; Department of Electrical Engineering, University of Arkansas, Fayetteville, Arkansas 72701 ; Kamto, A. ; Liu, Y. ; Burkett, S.L.
more authors

Your organization might have access to this article on the publisher's site. To check, click on this link: 

The formation of through-silicon vias (TSVs) provides a vertical interconnect scheme that can be used in three-dimensional stacking technologies. A sloped via sidewall is essential for conformal coverage of via lining materials deposited in subsequent steps that provide insulation (SiO2), barrier (TaN), and metal seed (Cu) layers. In this article, via sidewall angles in the range of 83°–90° are investigated resulting in variable degrees of conformal lining of the insulation, barrier, and seed layers. Via insulation is deposited by plasma enhanced chemical vapor deposition, while barrier and seed layers are deposited by sputtering. A modified Bosch process, using a deep reactive ion etch tool, allows formation of differing via profiles in silicon substrates. Cross-sectional views of via profiles showing the coverage of lining materials (SiO2, TaN, and Cu) are examined with a scanning electron microscope. For a constant via sidewall angle, variable aspect ratios allow us to determine the specific via profile that can be conformally lined and filled by Cu electroplating without the presence of voids. The aspect ratios of the vias under study are in the range of 2–4. Electrical performance of the fabricated TSVs is reported and is consistent with expected performance.

Published in:

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures  (Volume:26 ,  Issue: 6 )