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An On-Chip Loopback Block for RF Transceiver Built-In Test

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4 Author(s)
Onabajo, M. ; Dept. of Electr. & Comput. Eng., Texas A&M Univ., College Station, TX ; Silva-Martinez, J. ; Fernandez, F. ; Sanchez-Sinencio, E.

This brief addresses the realization of an on-chip block for built-in testing of RF transceivers with the loopback method. Design issues and measurement results are discussed, giving practical insights into closing the signal path between transmitter (Tx) and receiver (Rx) sections. The circuit is intended for cost-efficient production testing of RF front-end blocks with on-chip power detectors and bit-error-rate analysis at baseband frequencies for integrated transceivers operating in the 1.9- to 2.4-GHz range. It can provide 40-200 MHz Tx-Rx frequency shifting and 26-42 dB continuous attenuation while consuming a 0.052-mm2 die area in 0.13-mum CMOS technology and ~ 12 mW of power when activated in test mode.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:56 ,  Issue: 6 )

Date of Publication:

June 2009

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