By Topic

An On-Chip Loopback Block for RF Transceiver Built-In Test

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Onabajo, M. ; Dept. of Electr. & Comput. Eng., Texas A&M Univ., College Station, TX ; Silva-Martinez, J. ; Fernandez, F. ; Sanchez-Sinencio, E.

This brief addresses the realization of an on-chip block for built-in testing of RF transceivers with the loopback method. Design issues and measurement results are discussed, giving practical insights into closing the signal path between transmitter (Tx) and receiver (Rx) sections. The circuit is intended for cost-efficient production testing of RF front-end blocks with on-chip power detectors and bit-error-rate analysis at baseband frequencies for integrated transceivers operating in the 1.9- to 2.4-GHz range. It can provide 40-200 MHz Tx-Rx frequency shifting and 26-42 dB continuous attenuation while consuming a 0.052-mm2 die area in 0.13-mum CMOS technology and ~ 12 mW of power when activated in test mode.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:56 ,  Issue: 6 )