By Topic

Impact of Line-Edge Roughness on Double-Gate Schottky-Barrier Field-Effect Transistors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Shimeng Yu ; Inst. of Microelectron., Peking Univ., Beijing ; Yuning Zhao ; Lang Zeng ; Gang Du
more authors

The impact of line-edge roughness (LER) on double-gate (DG) Schottky-barrier field-effect transistors (SBFETs) in the level of device and circuit was investigated by a statistical simulation. The LER sequence is statistically generated by a Fourier analysis of the power spectrum of the Gaussian autocorrelation function. The results show that SBFETs are more sensitive to the LER effect in the high-V gs region and less sensitive in the subthreshold region compared with DG FinFETs. The aggressive fluctuation of drive current can be attributed to the variation of tunneling barrier width. Lowering the Schottky-barrier height and increasing the silicon-body thickness can suppress the parameter fluctuations from the LER effect. The simulation also shows that a 6T SRAM cell consisting of SBFETs is more vulnerable to noise disturbance than its counterpart consisting of FinFETs, particularly for the read operation, which is due to a larger mismatch of drivability of SBFETs within the cell.

Published in:

Electron Devices, IEEE Transactions on  (Volume:56 ,  Issue: 6 )