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I/sub DDQ/ test and diagnosis of CMOS circuits

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2 Author(s)
Isern, E. ; Dept. d''Enginyeria Electron., Univ. Politecnica de Catalunya, Barcelona, Spain ; Figueras, J.

Designers must target realistic faults if they desire high-quality test and diagnosis of CMOS circuits. The authors propose a strategy for generating high-quality I/sub DDQ/ test patterns for bridging faults. They use a standard ATPG tool for stuck-at faults that adapts to target bridging faults via I/sub DDQ/ testing. The authors discuss I/sub DDQ/ test set diagnosis capability and specifically generated vectors that can improve diagnosability, and provide test and diagnosis results for benchmark circuits.

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Design & Test of Computers, IEEE  (Volume:12 ,  Issue: 4 )