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Half-sine acceleration-shock is prescribed to the supports of the printed circuit board (PCB) in the JEDEC JESD22-B111 test standard, which is used to evaluate the reliability of the board level solder joints to mechanical shock. In practice, it is near impossible to introduce an acceleration-shock of perfect half-sine and distorted excitations are common. This inconsistency is believed to be responsible for the poor reproducibility of the JEDEC test, yet there has been no serious attempt to investigate the effects of such distortion to the responses of the PCB. In this article, the distortion of the excitation was quantified and analytical solutions were developed for the distorted PCB responses by expressing the distorted excitation using Fourier series of odd function. The magnitude of distortion in the response of the PCB-measured by the percentage deviation in the amplitude of the distorted response from the ideal response-was found to be quantitatively equivalent to the magnitude of distortion in the half-sine excitation-measured by the percentage deviation in the enclosed area of the distorted excitation from the ideal half-sine excitation. Without proper control of the quality of the half-sine excitation, drop tests based on JEDEC JESD22-B111 performed at two different sites could produce PCB responses that are significantly different. To improve the reproducibility of the test, the surface strain on the PCB should be specified as the key test parameter, supplemented by the half-sine acceleration-shock of specified duration, leaving the amplitude adjustable to meet the desired surface strain on the PCB.
Date of Publication: May 2009