Referenced Items are not available for this document.
The authors present a novel architecture designed to reduce the storage for decision vectors at the traceback block in the Viterbi decoder. By decreasing the rate of decision vector generation, the data storage requirement has been reduced by 29.9% in the proposed architecture compared to conventional traceback Viterbi decoders. The overall area has been reduced by ~25% when implemented in VLSI
Published in:
Electronics Letters
(Volume:32
,
Issue:
8
)
Date of Publication: 11 Apr 1996
- Page(s):
- 733 - 735
- ISSN :
- 0013-5194
- INSPEC Accession Number:
- 5251398
- Digital Object Identifier :
- 10.1049/el:19960478
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- 11 Apr 1996
- Sponsored by :
- Institution of Engineering and Technology
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
